This invention relates to a raster graphic display system, and more particularly, to an improved display memory organization and apparatus for accessing the display memory.
Raster scan CRT displays form a principal communication link between computer users and their hardware/software systems. The basic display device for computer-generated raster graphics is the CRT monitor which is closely related to a standard television receiver. To achieve the full potential of raster graphic systems, such systems require digital computational support substantially in excess of that provided by the typical CRT monitor. The development of large-scale integrated circuits and microcomputers makes it possible to control such displays at affordable prices. Typically, each picture element (pixel) of a substantially rectangular array of such elements of a CRT comprising the raster is assigned a unique address, which address is comprised of the x and y coordinates of each pixel in the array. Information to control the display of a pixel, its color and intensity, pixel control information, is stored in a random-access pixel memory at a location having an address corresponding to that of the pixel. The source of such pixel control information is typically a microcomputer located in a graphic controller. Such pixel control information may include the address in a color look-up memory at which location there is stored binary control signals which are used to control the intensity and color of each pixel of the array as it is scanned. In existing systems, the display memory (which includes the pixel memory) has been contiguous. In other words, if there are fifty pixels on a display line, the address of the first pixel on the first line would be 0, the address of the second pixel would be 1, the address of the third pixel would be 2, . . . , and the address of the first pixel on the second line would be 50. In order to determine the display memory address of the 49th pixel on the 102nd line, the following algorithm, 50 times 102 plus 49 would need to be calculated. Multiplication typically is one of the slowest of the instructions in any microprocessor. Characters to be displayed on a CRT are transferred from a font memory to the display memory. Such a transfer operation would require a multiple number of writes into display memory, with the corresponding address calculation (e.g., for a character of 16 lines, 16 address calculations and 16 writes into display memory would be required). Similarly, drawing vertical lines would require multiple address calculations and a corresponding write of the display memory. Also, some existing systems will blank the CRT display when writing to the display memories during the scan of the active display area, or only allow writing to the display memories during the retrace times.
Thus, there is a need for a display memory organization, and associated apparatus for accessing the display memory, which provides a more time efficient manner to load the display memory with the character(s) to be displayed on the CRT, a more efficient way to generate the graphics (more specifically, for the generation of vertical lines for display), and providing a way of accessing the display memory without resulting in blanking the display.